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UCD9222-EP www.ti.com slvsby1 ? october 2013 digital pwm system controller with 4-bit, 6-bit, or 8-bit vid support check for samples: UCD9222-EP 1 features 2 ? fully configurable two-output non-isolated ? over and under-voltage fault protection dc/dc pwm controller with support for ? over-temperature fault protection tms320c6670 ? and tms320c6678 ? dsp vid ? enhanced nonvolatile memory with error interface correction code (ecc) ? supports switching frequencies up to 2mhz ? device operates from a single supply with an with 250 ps duty-cycle resolution internal regulator controller that allows ? up to 1mv closed loop resolution operation over a wide supply voltage range ? hardware-accelerated, 3-pole/3-zero ? supported by fusion digital power ? compensator with non-linear gain for designer, a full featured pc based design improved transient performance tool to simulate, configure, and monitor ? supports multiple soft-start and soft-stop power supply performance. configurations including prebias start-up applications ? supports voltage margining and sequencing ? networking equipment ? sync in/out pins align dpwm clocks between multiple ucd92xx devices ? telecommunications equipment ? 12-bit digital monitoring of power supply ? fpga, dsp, and memory power parameters including: supports defense, aerospace, ? input current and voltage and medical applications ? output current and voltage ? controlled baseline ? temperature at each power stage ? one assembly and test site ? auxiliary adc inputs ? one fabrication site ? multiple levels of over-current fault protection: ? available in extended ( ? 55 c to 115 c) temperature range ? external current fault inputs ? extended product life cycle ? analog comparators monitor current sense voltage ? extended product-change notification ? current continually digitally monitored ? product traceability description the ucd9222 is a two-rail synchronous buck digital pwm controller designed for non-isolated dc/dc power applications. this device integrates dedicated circuitry for dc/dc loop management with support for up to two vid interfaces. additionally, the ucd9222 has flash memory and a serial interface to support configurability, monitoring and management. several voltage identification (vid) modes are supported, including a 4-bit parallel interface, a 6-bit interface and an 8-bit serial interface. the ucd9222 was designed to provide a wide variety of desirable features for non-isolated dc/dc converter applications while minimizing the total system component count by reducing external circuits. the solution integrates multi-loop management with sequencing, margining and tracking to optimize for total system efficiency. additionally, loop compensation and calibration are supported without the need to add external components. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 tms320c6670, tms320c6678, fusion digital power, auto-id are trademarks of texas instruments. production data information is current as of publication date. copyright ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
UCD9222-EP slvsby1 ? october 2013 www.ti.com to facilitate configuring the device, the texas instruments fusion digital power ? designer is provided. this pc based graphical user interface offers an intuitive interface to the device. this tool allows the design engineer to configure the system operating parameters for the application, store the configuration to on-chip non-volatile memory and observe both frequency domain and time domain simulations for each of the power stage outputs. ti has also developed multiple complementary power stage solutions ? from discrete drivers in the ucd7k family to fully tested power train modules in the ptd family. these solutions have been developed to complement the ucd92xx family of system power controllers. 2 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links : UCD9222-EP
UCD9222-EP www.ti.com slvsby1 ? october 2013 this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ordering information operating temperature orderable part pin top side supply package vid number range, t j number count marking ? 55 c to 115 c ucd9222wrgzrep 48-pin reel of 2500 qfn ucd9222ep v62/13622-01xe absolute maximum ratings (1) over operating free-air temperature range (unless otherwise noted) value unit voltage applied at v 33d to dgnd ? 0.3 to 3.8 v voltage applied at v 33a to agnd ? 0.3 to 3.8 v voltage applied to any pin (2) ? 0.3 to 3.8 v storage temperature (t stg ) ? 55 to 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltages referenced to gnd. recommended operating conditions over operating free-air temperature range (unless otherwise noted) min nom max unit v supply voltage during operation, v 33d , v 33dio , v 33a 3 3.3 3.6 v t j operating junction temperature range ? 55 115 c maximum junction temperature 125 c thermal information UCD9222-EP thermal metric (1) rgz units 48 pins ja junction-to-ambient thermal resistance (2) 27.1 jctop junction-to-case (top) thermal resistance (3) 12.9 jb junction-to-board thermal resistance (4) 4.3 c/w jt junction-to-top characterization parameter (5) 0.2 jb junction-to-board characterization parameter (6) 4.3 jcbot junction-to-case (bottom) thermal resistance (7) 0.6 (1) for more information about traditional and new thermal metrics, see the ic package thermal metrics application report, spra953 . (2) the junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a jedec-standard, high-k board, as specified in jesd51-7, in an environment described in jesd51-2a. (3) the junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. no specific jedec- standard test exists, but a close description can be found in the ansi semi standard g30-88. (4) the junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the pcb temperature, as described in jesd51-8. (5) the junction-to-top characterization parameter, jt , estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining ja , using a procedure described in jesd51-2a (sections 6 and 7). (6) the junction-to-board characterization parameter, jb , estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining ja , using a procedure described in jesd51-2a (sections 6 and 7). (7) the junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. no specific jedec standard test exists, but a close description can be found in the ansi semi standard g30-88. spacer copyright ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links : UCD9222-EP
UCD9222-EP slvsby1 ? october 2013 www.ti.com electrical characteristics over operating junction temperature range (unless otherwise noted) parameter test conditions min nom max unit supply current i v33 total v33 supply current, 54 80 ma v 33a = v 33dio = 3.3 v i v33dio v 33dio = 3.3 v 42 55 ma supply current i v33a v 33a = 3.3 v 8 15 ma i v33dio v 33dio = 3.3 v storing configuration 52 65 ma parameters in flash memory internal regulator controller inputs/outputs v 33 3.3-v linear regulator emitter of npn transistor 3.25 3.3 3.6 v v 33fb 3.3-v linear regulator feedback 4 4.6 v i v33fb series pass base drive v in = 12 v 0.2 0.4 8 ma beta series npn pass device 40 100 externally supplied 3.3 v power v 33d , v 33dio1 , digital 3.3-v power t j = 25 c 3.0 3.6 v v 33dio2 v33a analog 3.3-v power t j = 25 c 3.0 3.6 v error amplifier inputs eapn, eann v cm common mode voltage each pin 0 1.8 v v error internal error voltage range afe_gain field of cla_gains = 1x (1) ? 256 248 mv eap-ean error voltage digital resolution afe_gain field of cla_gains = 8x 1 mv r ea input impedance ground reference, t j = 25 c 1.5 m ? i offset input offset current 1 k ? source impedance, t j = 25 c ? 5 5 a vref 10-bit dac v ref reference voltage setpoint 0 1.7 v v refres reference voltage resolution 1.56 mv analog inputs cs1a, cs2a, vinmon, iinmon, vtrack, temp1, temp2, addr0, addr1 v adc_range measurement range for voltage inputs: vinmon, iinmon, vtrack, temp1, 0 2.6 v monitoring temp2, cs1a, cs2a voffset input offset voltage ? 27 27 mv v oc_thrs over-current comparator threshold inputs: cs1a, cs2a 0.032 2 v voltage range (2) v oc_res over-current comparator threshold inputs: cs1a, cs2a 31.25 mv voltage range temp internal internal temperature sense over range from 0 c to 100 c ? 15 15 c accuracy inl adc integral nonlinearity t j = -40 c to 115 c ? 2.5 2.5 mv i lkg input leakage current 3 v applied to pin 100 na r in input impedance ground reference 8 m ? c in current sense input capacitance 10 pf (1) see the ucd92xx pmbus command reference for the description of the afe_gain field of cla_gains command. (2) can be disabled by setting to ' 0 ' 4 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links : UCD9222-EP
UCD9222-EP www.ti.com slvsby1 ? october 2013 electrical characteristics (continued) over operating junction temperature range (unless otherwise noted) parameter test conditions min nom max unit digital inputs/outputs dgnd v ol low-level output voltage i ol = 6 ma (1) , v 33dio = 3 v v +0.3 v 33dio v oh high-level output voltage i oh = -6 ma (2) , v 33dio = 3 v v ? 0.6v v ih high-level input voltage v 33dio = 3v 2.1 3.6 v v il low-level input voltage v 33dio = 3.5 v 1.4 v system performance v reset voltage where device comes out of reset v 33d pin 2.3 2.4 v t reset pulse width needed for reset nreset pin 2 s vref commanded to be 1v, at 25 c afegain = 4, setpoint reference accuracy ? 10 10 mv 1v input to eap/n measured at output of the eadc (3) v refacc setpoint reference accuracy over ? 55 c to 115 c ? 40 40 mv temperature afegain = 4 compared to v diffoffset differential offset between gain settings ? 4 4 mv afegain = 1, 2, or 8 240 + 1 t delay digital compensator delay 240 switching ns cycle f sw switching frequency 15.260 2000 khz accuracy ? 5% 5% duty maximum and minimum duty cycle 0% 100% v33 slew rate between 2.3v and 2.9v,t j = -40 c v 33 slew minimum v 33 slew rate 0.25 v/ms to 115 c t retention retention of configuration parameters (4) t j = 25 c 100 years write_cycles number of nonvolatile erase/write cycles t j = 25 c 20 k cycles all rails configured to accept 4-bit vid messages (5) 1 rate vid max vid message rate all rails configured to accept 6-bit vid messages (5) 4 msg/msec all rails configured to accept 8-bit vid messages (6) 4 (1) the maximum i ol , for all outputs combined, should not exceed 12 ma to hold the maximum voltage drop specified. (2) the maximum i oh , for all outputs combined, should not exceed 48 ma to hold the maximum voltage drop specified. (3) with default device calibration. pmbus calibration can be used to improve the regulation tolerance. (4) the data retention specification is based on accelerated stress testing at 170 c for 420 hours and using an arrhenius model with activation energy of 0.6 ev. (5) vid message rate on each interface. measured over a 1.0 msec interval (6) vid message rate on pmbus interface. copyright ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links : UCD9222-EP
UCD9222-EP slvsby1 ? october 2013 www.ti.com adc monitoring intervals and response times the adc operates in a continuous conversion sequence that measures each rail ' s output voltage and output current, plus six other variables (input voltage, input current, internal temperature, tracking source, and two external temperature sensors). the length of the sequence is determined by the number of output rails (numrails) configured for use. the time to complete the monitoring sampling sequence is give by the formula: t adc_seq = t adc (2 numrails + 6) parameter test conditions min typ max unit t adc adc single-sample time 3.84 s t adc_seq adc sequencer interval min = 2 1 rail + 6 = 8 samples 30.72 38.40 s max = 2 2 rails + 6 = 10 samples the most recent adc conversion results are periodically converted into the proper measurement units (volts, amperes, degrees), and each measurement is compared to its corresponding fault and warning limits. the monitoring operates asynchronously to the adc, at intervals shown in the table below. parameter test conditions min typ max unit t vout output voltage monitoring interval 200 s t iout output current monitoring interval 200 n rails s t vin input voltage monitoring interval 1 ms t iin input current monitoring interval 1 ms t temp temperature monitoring interval 100 ms t auxadc auxiliary adc monitoring interval 100 ms because the adc sequencer and the monitoring comparisons are asynchronous to each other, the response time to a fault condition depends on where the event occurs within the monitoring interval and within the adc sequence interval. once a fault condition is detected, some additional time is required to determine the correct action based on the fault_response code, and then to perform the appropriate response. the following table lists the worse-case fault response times. max max parameter test conditions typ unit no vid /w vid (1) t ovf , over-/under-voltage fault response time normal regulation, no pmbus activity, 250 800 s t uvf during normal operation 4 stages enabled t ovf , over-/under-voltage fault response time, during data logging to nonvolatile 800 1000 s t uvf during data logging memory (2) t ovf , over-/under-voltage fault response time, during tracking and soft-start ramp. 400 s t uvf when tracking or sequencing enable t ocf , over-/under-current fault response time normal regulation, no pmbus activity, 100 + 5000 s t ucf during normal operation 4 stages enabled 75% to 125% current (600 nrails) step (3) t ocf , over-/under-current fault response time, during data logging to nonvolatile 600 + 5000 s t ucf during data logging memory 75% to 125% current step (600 nrails) t otf over-temperature fault response time temperature rise of 10 c/sec, at ot 1.60 sec threshold t 3-state time to tristate the pwm output after a driver_config = 0x01 5.5 s shutdown is initiated (1) controller receiving vid commands at a rate of 4000 msg/sec. (2) during a store_default_all command, which stores the entire configuration to nonvolatile memory, the fault detection latency can be up to 10 ms. (3) because the current measurement is averaged with a smoothing filter, the response time to an over-current condition depends on a combination of the time constant ( ) from table 3 , the recent measurement history, and how much the measured value exceeds the over-current limit. 6 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links : UCD9222-EP
UCD9222-EP www.ti.com slvsby1 ? october 2013 hardware fault detection latency the controller contains hardware fault detection circuits that are independent of the adc monitoring sequencer. parameter test conditions max time unit time to disable dpwm output base on active fault pin t fault high level on fault pin 18 s signal time to disable the dpwm a output based on internal switch t clf step change in cs voltage from 0v to 2.5v 4 analog comparator cycles pmbus/smbus/i 2 c the timing characteristics and timing diagram for the communications interface that supports i2c, smbus and pmbus are shown below. figure 1. i 2 c/smbus/pmbus timing in extended mode diagram i 2 c/smbus/pmbus timing requirements t j = ? 55 c to 115 c, 3 v < v 33 < 3.6 v, typical values at t j = 25 c parameter test conditions min typ max unit f smb smbus/pmbus operating frequency slave mode; smbc 50% duty cycle 10 1000 khz f i2c i c operating frequency slave mode; scl 50% duty cycle 10 1000 khz t (buf) bus free time between start and stop 5 s t (hd:sta) hold time after (repeated) start 0.3 s t (su:sta) repeated start setup time 0.3 s t (su:sto) stop setup time 0.3 s t (hd:dat) data hold time receive mode 0 ns t (su:dat) data setup time 55 ns t (timeout) error signal/detect see (1) 35 ms t (low) clock low period 0.55 s t (high) clock high period see (2) 0.3 50 s t (low:sext) cumulative clock low slave extend time see (3) 25 ms t fall clock/data fall time rise time t rise = v ilmax ? 0.15) to (v ihmin + 0.15) , 1000 ns t j = -40 c to 115 c (1) the ucd9222 times out when any clock low exceeds t (timeout) . (2) t (high) , max, is the minimum bus idle time. smbc = smbd = 1 for t > 50 ms causes reset of any transaction involving ucd9222 that is in progress. (3) t (low:sext) is the cumulative time a slave device is allowed to extend the clock cycles in one message from initial start to the stop. copyright ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links : UCD9222-EP
UCD9222-EP slvsby1 ? october 2013 www.ti.com i 2 c/smbus/pmbus timing requirements (continued) t j = ? 55 c to 115 c, 3 v < v 33 < 3.6 v, typical values at t j = 25 c parameter test conditions min typ max unit t rise clock/data rise time fall time t fall = 0.9 v 33 to (v ilmax ? 0.15) , t j = - 1000 ns 40 c to 115 c c in functional block diagram 8 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links : UCD9222-EP 12-bit adc 260 ksps osc arm-7 core eap2 ean2 cs1a cs2a vinmon iinmon/auxadc4 vtrack/auxadc3 temp2/auxadc2 temp1/auxadc1 v33x xgnd analog front end (afe) ref adc 6 bit iir 3p/3z err amp eap1 ean1 coeff. regs compensator analog front end por/bor ref 1 analog comparators oc dpwm1 pmbus_clk pmbus_data pmbus_alert pmbus_cntrl 5 6 bpcap vid1a vid1b vid1c vid1s vid2a vid2b vid2c vid2s vid 1 - 2 compensator 3p/3z iir flash memory with ecc diff amp fusion power peripheral 2 fusion power peripheral 1 internal temp sense 3.3v reg. controller & 1.8v regulator ref 2 digital high res pwm digital high res pwm tcktdi tdo tms rck ntrst oc dpwm2 nreset addr0 addr1 dpwm2a flt2a dpwm1a flt1a syncin/jtag_tdi syncout/jtag_tdo jtag powergood pg1 pg2 en1 en2 gpio pmbus
UCD9222-EP www.ti.com slvsby1 ? october 2013 (1) in case of conflict between figure 2 and table 1 the table shall take precedence (2) preliminary versions of this data sheet prior to june 14, 2010 had a different definition for pins 17, 18, and 21. board designs made with that earlier pinout should be updated. figure 2. pin assignment diagram copyright ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links : UCD9222-EP temp1/auxadc1 vtrack/auxadc3 48 47 46 45 44 43 42 41 40 39 33 32 31 30 29 28 27 26 25 13 14 15 18 19 21 16 17 3 4 5 6 7 8 9 10 11 12 34 22 20 nreset vinmon vid1s vid2s pmbus_data flt2a pmbus_clk dpwm1a pg1 vid1c dpwm2a pg2 vid1a pmbus_alert pmbus_cntrl vid2a vid1b jtag_tms jtag_ntrst adc_ref syncin/jtag_tdi syncout/jtag_tdo jtag_tck en2 en1 dgnd3 agnd3 ean2 eap2 pmbus_addr0 cs2a v33fb flt1a powergood pmbus_addr1 v33a cs1a v33dio 23 24 vid2b vid2c 38 37 ean1 eap1 1 2 temp2/auxadc2 iinmon/auxadc4 35 36 agnd2 bpcap
UCD9222-EP slvsby1 ? october 2013 www.ti.com table 1. pin functions pin no. pin label description 1 iinmon/auxadc4 input current monitor, or auxiliary adc input 4 2 temp2/auxadc2 temperature sense input for rail 2, or auxiliary adc input 2 3 cs2a power stage 2a current sense input and input to analog comparator 2 4 vinmon input voltage monitor 5 nreset active low device reset input. pull up to 3.3v with a 10k ohm resistor 6 flt1a fault indicator for stage 1a 7 vid1s vid select pin for rail 1 8 flt2a fault indicator for stage 2a 9 vid2s vid select pin for rail 2 10 pmbus_clk pmbus clock. pull up to 3.3v with a 2k ohm resistor 11 pmbus_data pmbus data. pull up to 3.3v with a 2k ohm resistor 12 dpwm1a digital pulse width modulator output 1a 13 pg1 rail 1 power good indicator 14 dpwm2a digital pulse width modulator output 2a 15 pg2 rail 2 power good indicator 16 vid1a vid input pin for rail 1 ? least significant bit 17 powergood power good indication 18 vid1b vid input pin for rail 1 19 pmbus_alert pmbus alert. pull up to 3.3v with a 10k ohm resistor 20 pmbus_cntrl pmbus control. pull up to 3.3v with a 10k ohm resistor 21 vid1c vid input pin for rail 1 ? most significant bit 22 vid2a vid input pin for rail 2 ? least significant bit 23 vid2b vid input pin for rail 2 24 vid2c vid input pin for rail 2 ? most significant bit 25 en1 rail 1 enable 26 en2 rail 2 enable 27 jtag_tck jtag test clock 28 syncout/jtag_tdo mux'ed pin jtag test data output, dpwm sync output 29 syncin/jtag_tdi mux'ed pin ? jtag test data in, dpwm sync input 30 jtag_tms jtag test mode select. pull up to 3.3v with a 10k ohm resistor 31 (jtag) ntrst jtag test reset ? tie to ground with a 10k ohm resistor 32 dgnd3 digital ground 33 v33dio 3.3v supply for digital i/o and core 34 v33a analog 3.3v supply 35 bpcap 1.8v bypass capacitor ? tie 0.1 f cap to analog ground 36 agnd2 analog ground 37 eap1 error analog, differential voltage, positive channel 1 input 38 ean1 error analog, differential voltage, negative channel 1 input 39 eap2 error analog, differential voltage, positive channel 2 input 40 ean2 error analog, differential voltage, negative channel 2 input 41 v33fb connection to the base of 3.3v linear regulator transistor (no connect if unused) 42 cs1a power stage 1a current sense input and input to analog comparator 1 43 addr1 pmbus address sense. channel 1. 44 addr0 pmbus address sense. channel 0. 45 vtrack/auxadc3 tracking voltage input, or auxiliary adc input 3 46 temp1/auxadc1 temperature sense input for rail 1, or auxiliary adc input 1 47 agnd3 analog ground 10 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links : UCD9222-EP
UCD9222-EP www.ti.com slvsby1 ? october 2013 table 1. pin functions (continued) pin no. pin label description 48 adc_ref adc reference. tie to analog ground through 0.1 f capacitor powerpad it is recommended that this pad be connected to analog ground typical application schematic figure 3 shows the ucd9222 power supply controller as part of a system that provides the regulation of two independent power supplies. the loop for each power supply is created by the respective voltage outputs feeding into the differential voltage error adc (eadc) inputs, and completed by dpwm outputs feeding into the gate drivers for each power stage. the v sense rail signals must be routed to the eap/ean input that matches the dpwm number that controls the output power stage. for example, the power stage driven by dpwm1a must have its feedback routed to eap1 and ean1. figure 3. typical application schematic copyright ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links : UCD9222-EP ucd7242 ucd9222
UCD9222-EP slvsby1 ? october 2013 www.ti.com functional overview the ucd9222 contains two fusion power peripherals (fpp). each fpp consists of: ? a differential input error voltage amplifier. ? a 10-bit dac used to set the output regulation reference voltage. ? a fast adc with programmable input gain to digitally measure the error voltage. ? a dedicated 3-pole/3-zero digital filter to compensate the error voltage ? a digital pwm (dpwm) engine that generates the pwm pulse width based on the compensator output. each controller is configurable through the pmbus serial interface. pmbus interface the pmbus is a serial interface specifically designed to support power management. it is based on the smbus interface that is built on the i 2 c physical specification. the ucd9222 supports revision 1.2 of the pmbus standard. wherever possible, standard pmbus commands are used to support the function of the device. for unique features of the ucd9222, mfr_specific commands are defined to configure or activate those features. these commands are defined in the ucd92xx pmbus command reference . the ucd9222 is pmbus compliant, in accordance with the "compliance" section of the pmbus specification. the firmware is also compliant with the smbus 2.0 specification, including support for the smbus alert function. the hardware can support 100 khz, 400 khz, or 1 mhz pmbus operation. resistor programmed pmbus address decode the pmbus address is selected using resistors attached to the addr0 and addr1 pins. at power-up, the device applies a bias current to each address detect pin. the measured voltage on each pin determines the pmbus address as defined in table 2 . for example, a 133k resistor on addr1 and a 75k on addr0 will select pmbus address = 100. resistors are chosen from the standard eia-e96 series, and should have accuracy of 1% or better. figure 4. pmbus address detection method a short or open on either address pin causes the pmbus address to default to address 126. to avoid potential conflicts between multiple devices, it is best to avoid using address 126. some addresses should be avoided; see table 2 for details. 12 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links : UCD9222-EP v33 to 12 -bit adc resistor toset pmbus address ucd9222 addr - 0, addr - 1 pins 10 a i m bias
UCD9222-EP www.ti.com slvsby1 ? october 2013 table 2. pmbus address bins (1) addr0 (short) (open) 42.2k 48.7k 56.2k 64.9k 75k 86.6k 100k 115k 133k 154k 178k 205k < 36.5k > 237k < 36.5k 126 126 126 126 126 126 126 126 126 126 126 126 126 126 (short) 42.2k 126 126 (2) 1 2 3 4 5 6 7 8 9 10 11 (3) 126 48.7k 126 126 (2) 13 14 15 16 17 18 19 20 21 22 33 126 56.2k 126 24 25 26 27 28 29 30 31 32 33 34 35 126 64.9k 126 36 37 38 39 40 41 42 43 44 45 46 47 126 75k 126 48 49 50 51 52 53 54 55 56 57 58 59 126 86.6k 126 60 61 62 63 64 65 66 67 68 69 70 71 126 100k 126 72 73 74 75 76 77 78 79 80 81 82 83 126 115k 126 84 85 86 87 88 89 90 91 92 93 94 95 126 133k 126 96 97 98 99 100 101 102 103 104 105 106 107 126 154k 126 108 109 110 111 112 113 114 115 116 117 118 119 126 178k 126 120 121 122 123 124 125 126 126 (2) 126 126 126 126 126 205k 126 126 126 126 126 126 126 126 126 126 126 126 126 126 > 237k 126 126 126 126 126 126 126 126 126 126 126 126 126 126 (open) (1) shaded addresses are not recommended as they will cause conflict when multiple devices are used. (2) reserved. do not use. (3) conflicts with rom. do not use. vid interface the ucd9222 supports vid (voltage identification) inputs from up to two external vid enabled devices. the vid codes may be 4-, 6-, or 8-bit values; the format is selected using the vid_config pmbus command. in 4- and 6-bit mode, each host uses four vid input signals (vid_a, vid_b, vid_c, and vid_s) to send vid codes to the ucd9222. in 8-bit mode, the pmbus input is used to receive vid commands from the vid devices ? i 2 c interfaces. figure 5. one ucd9222 controlled by two dsp/asics using 4-bit or 6-bit vid format regardless of which vid mode is used, the commanded output voltage reference is set according to this formula: vref_cmd = (vid_code vid_slope) + vid_offset, where vid_slope = (vid_vout_high ? vid_vout_low) / ((2^vid_format) -1), and vid_offset = vid_vout_low. copyright ? 2013, texas instruments incorporated submit documentation feedback 13 product folder links : UCD9222-EP ucd9222 vid1a vid2a vid1b vid2b vid1c vid2c vid1s vid2s vid device #1 vcntl[0] vcntl[1] vcntl[2] vcntl[3] vid device #2 vcntl[0]vcntl[1] vcntl[2] vcntl[3] addr1
UCD9222-EP slvsby1 ? october 2013 www.ti.com the vid_vout_high, vid_vout_low, and vid_format values are set using the vid_config pmbus command. the same command is used to set the initial vid code that will be used at power-up. in addition, the vid_config command also sets the initial voltage that the device ramps to at the end of the soft start; and defines a lockout interval over which the vid is ignored during the soft start. vid lockout interval: because the vid signals may be originating from a device that is being powered by the ucd9222, the voltage levels on the vid signal may not be valid logic levels until the supply voltage at the powered device has stabilized. for this reason a configurable lockout interval is applied each time the regulated output voltage is turned on. the lockout interval timer starts when the output voltage reaches the top of the soft- start ramp. positive values range from 1 to 32767 ms, with 1 ms resolution. a value of 0 will enable the vid inputs immediately at the top of the start ramp. negative values disable the lockout, allowing the vid inputs to remain active all the time regardless of the output voltage state. the default value is 0. 4-bit vid mode: in 4-bit vid mode, the four vid input signals are used to provide the four bits of vid data, as shown in the table below. the vid lines are level-sensitive, and are periodically polled every 400 s. when the vid lines are changed to command a new voltage, there may be a delay of 500 to 600 s while the ucd9222 confirms that the vid signal levels are stable. the output voltage will then slew to the new setpoint voltage at the rate specified by the pmbus vout_transition_rate command. pin purpose rail 1 rail 2 vid_a data bit 0 (least significant bit) vid1a vid2a vid_b data bit 1 vid1b vid2b vid_c data bit 2 vid1c vid2c vid_s data bit 3 (most significant bit) vid1s vid2s 6-bit vid mode: in 6-bit vid mode, the four vid input signals are used to provide the six bits of vid data, as shown in the table below. each of the three data lines (vid_a, vid_b, and vid_c) carries two bits of data per vid code. the bits are clocked and selected by the vid_s select line. pin purpose rail 1 rail 2 vid_a data bit 0 when vid_s is low, vid1a vid2a data bit 3 when vid_s is high vid_b data bit 1 when vid_s is low, vid1b vid2b data bit 4 when vid_s is high vid_c data bit 2 when vid_s is low, vid1c vid2c data bit 5 when vid_s is high vid_s select line: vid1s vid2s low= lsb, high = msb 14 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links : UCD9222-EP
UCD9222-EP www.ti.com slvsby1 ? october 2013 the falling edge of the vid_s line triggers the ucd9222 to read bits 2:0 on the three vid data lines. the rising edge of vid_s triggers the ucd9222 to read bits 5:3 on the three vid data lines and calculate a new vout setpoint. this calculation takes from 35 to 135 s. the output voltage will then slew to the new setpoint voltage at the rate specified by the vout_transition_rate pmbus command. figure 6. 6-bit vid data transfer the set-up time on the data lines is 0 s. all four vid lines must hold at the same level for some time after a change in the vid_s line to allow the ucd9222 to read and validate the data signals and perform necessary voltage calculations. the ucd9222 can tolerate single hold times as short as 70 s, but does not have sufficient computation power to sustain continuous vid messaging that quickly. it is expected that the hold time will be at least 125 s for sustained operations. it is recommended that the dsp only send vid messages when the regulated voltage needs to change; sending the same vid code repeatedly and continuously provides no benefit. figure 7 and table 3 illustrate the critical timing measurements as they apply to the 6-bit vid interface. figure 7. 6-bit vid timing copyright ? 2013, texas instruments incorporated submit documentation feedback 15 product folder links : UCD9222-EP vid_s tf tr thd tsu tchi tclo vid_a,vid_b, vid_c vout tvo lower half vid_a = bit 0 vid_b = bit 1vid_c = bit 2 vid_s vid_a vid_bvid_c upperhalf vid_a = bit 3 vid_b = bit 4vid_c = bit 5 lower half vid_a = bit 0 vid_b = bit 1vid_c = bit 2 upper half vid_a = bit 3 vid_b = bit 4vid_c = bit 5 vout
UCD9222-EP slvsby1 ? october 2013 www.ti.com table 3. 6-bit vid timing symbo parameter min typ max units l tr data and clock rise time ? 2.5 s tf data and clock fall time ? 0.3 s tsu data setup before changing clock 0 s thd data hold until next clock change 70 s tchi clock high time 70 125 s tclo clock low time 70 125 s tvo response time from rising edge of vid_s to start of 35 135 s vout slewing to new setpoint 8-bit vid mode: in 8-bit vid mode, the four vid input signals are not used. instead, an 8-bit vid code is transmitted to the ucd9222 through the pmbus / i2c port using one of the vid_code_railn commands, where n is the rail number from 1 to 2. name description (1) code vid_config selects the vid mode, sets the upper and lower voltage limits, and the starting voltage code at power-up. 0xbb vid_code_rail1 selects the vid code used to set the output voltage for rail 1. 0xbc vid_code_rail2 selects the vid code used to set the output voltage for rail 2. 0xbd (1) for a complete description of the serial vid commands, see the ucd92xx pmbus command reference ( sluu337 ) 16 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links : UCD9222-EP
UCD9222-EP www.ti.com slvsby1 ? october 2013 figure 8. pmbus timing for vid_code_railn command table 4. typical pmbus timing for vid_code_railn command @ 400khz symbol parameter conditions typ units t msgpec message transmit time, with pec 400 khz clock, pec enabled 162 ? 256 s message transmit time, without pec 400 khz clock, pec enabled 126 ? 221 t vo end of message until vout starts changing 28 ? 140 s t msgvo start of message until vout start changing 400 khz clock, pec disabled 169 ? 314 s the total time to transmit the serial vid command will vary depending on the other tasks that the ucd92xx processor is performing. typical packet times varied from 162 to 256 s when the pmbus is configured for a 400 kb/s transfer rate running and the optional pec byte is enabled. disabling the pec byte saves about 35 s and the transfer times are from 126 to 221 s. note that these are not specified best-case/worst-case timings, but indicate a range given the typical acknowledge overhead in the host and controller. after the vid packet has been received by the controller there is a delay before the set-point reference dac is updated. this delay time varies from ~28 s to 140 s (typical ) depending on the existing priority of updating set- point reference dac when the command is received. with a 221 s packet transfer time, it would seem possible to send 4500 vid messages per second to the device. very short bursts at this rate might be acceptable, but doing so for sustained periods could overwhelm the available processing resources in the ucd92xx, causing it to be delayed in performing its other monitoring and fault response tasks. in addition, if multiple hosts are trying to talk on the pmbus at such high rates then bus contention will occur with great regularity. to prevent these issues, it is prudent to limit the total vid messaging rate to less than 4 messages per millisecond. in a system with four independent hosts, each host might need to be limited to less than 1 message per millisecond. therefore, to minimize pmbus traffic, it is best to only issue the vid command when a voltage change is required. there is no benefit to sending the same vid code continuously and repeatedly. jtag interface the jtag interface can provide an alternate interface for programming the device. two of the jtag pins (tdi and tdo) are shared with the syncin and syncout function. jtag is disabled by default. there are three conditions under which the jtag interface is enabled: 1. when the rom_mode pmbus command is issued. 2. on power-up if the data flash is blank. this allows jtag to be used for writing the configuration parameters to a programmed device with no pmbus interaction. 3. when an invalid address is detected at power-up. by opening or shorting one of the address pins to ground, an invalid address can be generated that enables jtag. when the jtag port is enabled the shared pins are not available for use as sync pins. if jtag is to be used, an external mechanism such as jumpers or a mux must be used to prevent conflict between jtag and the sync pins. copyright ? 2013, texas instruments incorporated submit documentation feedback 17 product folder links : UCD9222-EP addr cmd data pec ack ack ack ack start stop pmbus clockpmbus data v out t msgvo t msg t vo
UCD9222-EP slvsby1 ? october 2013 www.ti.com bias supply generator (shunt regulator controller) the i/o and analog circuits in the ucd9222 require 3.3v to operate. this can be provided using a stand-alone external 3.3v supply, or it can be generated from the main input supply using an internal shunt regulator and an external transistor. regardless of which method is used to generate the 3.3v supply, bypass capacitors of 0.1 f and 4.7 f should be connected from v33a and v33d to ground near the device. an additional bypass capacitor from 0.1 to 1 f must be connected from the bpcap pin to ground for the internal 1.8v supply to the device ? s logic circuits. figure 9 shows a typical application using the external transistor. the base of the transistor is driven by a resistor r1 to vin and a transconductance amplifier whose output is on the v33fb pin. the npn emitter becomes the 3.3v supply for the chip. figure 9. 3.3v shunt regulator controller i/o in order to generate the correct voltage on the base of the external pass transistor, the internal transconductance amplifier sinks current into the v33fb pin and a voltage is produced across r1. this resistor value should be chosen so that isink is in the range from 0.2 to 0.4ma. r1 is defined as (1) where i sink is the current into the v33fb pin; v in is the power supply input voltage, typically 12v; i e is the current draw of the device and any pull up resistors tied to the 3.3v supply; and is the beta of the pass transistor. for i sink = 0.3 ma, v in =12v, =99, v be = 0.7v and i e =50ma, this formula selects r1 = 10k . weaker transistors or larger current loads will require less resistance to maintain the desired i sink current. for example, lowering to 40 would require r1 = 5.23 k ; likewise, an input voltage of 5v requires a value of 1.24 k for r1. power-on reset the ucd9222 has an integrated power-on reset (por) circuit that monitors the supply voltage. at power-up, the por circuit detects the v33d rise. when v33d is greater than v reset , the device initiates an internal startup sequence. at the end of the startup sequence, the device begins normal operation, as defined by the downloaded device pmbus configuration. external reset the device can be forced into the reset state by an external circuit connected to the nreset pin. a logic low voltage on this pin holds the device in reset. to avoid an erroneous trigger caused by noise, a 10k pull up resistor to 3.3v is recommended. 18 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links : UCD9222-EP ( ) in be 1 e sink v 3.3 v r i i 1 - - = + b + v33fb 0.1 r1 vin 4.7 0.1 fcx491a ucd9222 to power stage +3.3v +1.8v v33a v33d bpcap 0. 1
UCD9222-EP www.ti.com slvsby1 ? october 2013 on_off_config the on_off_config command is used to select the method of turning rails on and off. it can be configured so that the rail: ? stays off, ? turns on automatically, ? responds to the pmbus_cntrl pin, ? responds to operation command, or ? responds to logical-and of the pmbus_cntrl pin and the operation command. the on_off_config command also sets the active polarity of the pmbus_cntrl pin. en1/en2 in addition to the pmbus_cntrl pin supported by all ucd92xx products, the ucd9222 also supports separate enable pins for each rail. the polarity of the en1/en2 pin is user-configurable, and will be the same as the polarity chosen for the pmbus_cntrl pin by the on_off_config command. when the on_off_config setting is configured to respond the pmbus_cntrl pin, the pmbus_cntrl pin signal will be logically anded with the rail ? s en pin signal. pg1/pg2 in addition to the powergood output signal supported by all ucd92xx products, the ucd9222 also supports separate pg indicators for each rail. the powergood signal is the logical-and of all rails, while pg1 and pg2 indicate the status of a single rail. all three of these indicators are open-drain outputs, so they require pull-up resistors. when driving external circuits with logic voltages less than 3.3v, the pull-ups may be tied to that lower supply voltage, thus avoiding the need for level-shifters. output voltage adjustment the output voltage may be set to maintain a steady voltage or it may be controlled dynamically by the vid interface, depending on the vid_config setting. when not being commanded by the vid interface, the nominal output voltage is programmed by a combination of pmbus settings: vout_command, vout_cal_offset, vout_scale_loop, and vout_max. their relationship is shown in figure 10 . these pmbus parameters need to be set such that the resulting vref dac value does not exceed the maximum value of v ref . output voltage margining is configured by the vout_margin_high and vout_margin_low commands. the operation command selects between the nominal output voltage and either of the margin voltages. the operation command also includes an option to suppress certain voltage faults and warnings while operating at the margin settings. figure 10. pmbus voltage adjustment mechanisms copyright ? 2013, texas instruments incorporated submit documentation feedback 19 product folder links : UCD9222-EP vout_margin_high vout_cal_offset vout_margin_low vout_command + limiter 3:1 mux vout_ scale_ loop vref dac digital compensator eadc + v sense vout_ov_fault_limit vout_ov_warn_limit vout_uv_warn_limit vout_uv_fault_limit r1 r2 v out vout_max 3:1 mux vid_code_railx operation command 4-wire vid interface vid_config
UCD9222-EP slvsby1 ? october 2013 www.ti.com for a complete description of the commands supported by the ucd9222 see the ucd92xx pmbus command reference (sluu337). each of these commands can also be issued from the texas instruments fusion digital power ? designer program. this graphical user interface (gui) pc program issues the appropriate commands to configure the ucd9222 device. calibration to optimize the operation of the ucd9222, pmbus commands are supplied to enable fine calibration of output voltage, output current, and temperature measurements. the supported commands and related calibration formulas may be found in the ucd92xx pmbus command reference ( sluu337 ). analog front end (afe) figure 11. analog front end block diagram the ucd9222 senses the power supply output voltage differentially through the eap and ean pins. the error amplifier utilizes a switched capacitor topology that provides a wide common mode range for the output voltage sense signals. the fully differential nature of the error amplifier also ensures low offset performance. the output voltage is sampled at a programmable time (set by the eadc_sample_trigger pmbus command). when the differential input voltage is sampled, the voltage is captured in internal capacitors and then transferred to the error amplifier where the value is subtracted from the set-point reference which is generated by the 10-bit vref dac as shown in figure 11 . the resulting error voltage is then amplified by a programmable gain circuit before the error voltage is converted to a digital value by the error adc (eadc). this programmable gain is configured through the pmbus and affects the dynamic range and resolution of the sensed error voltage as shown in table 5 . the internal reference gains and offsets are factory-trimmed at the 4x gain setting, so it is recommended that this setting be used whenever possible. table 5. analog front end resolution afe_gain for effective adc digital error voltage afe gain pmbus command resolution (mv) dynamic range (mv) 0 1x 8 ? 256 to 248 1 2x 4 ? 128 to 124 2 (recommended) 4x 2 ? 64 to 62 3 8x 1 ? 32 to 31 the afe variable gain is one of the compensation coefficients that are stored when the device is configured by issuing the cla_gains pmbus command. compensator coefficients are arranged in several banks: one bank for start/stop ramp or tracking, one bank for normal regulation mode and one bank for light load mode. this allows the user to trade-off resolution and dynamic range for each operational mode. the eadc, which samples the error voltage, has high accuracy, high resolution, and a fast conversion time. however, its range is limited as shown in table 5 . if the output voltage is different from the reference by more than this, the eadc repo o rts a saturated value at ? 32 lsbs or 31 lsbs. the ucd9222 overcomes this limitation by adjusting the vref dac up or down in order to bring the error voltage out of saturation. in this way, the effective range of the adc is extended. when the eadc saturates, the vref dac is slewed at a rate of 0.156 v/ms, referred to the ea differential inputs. 20 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links : UCD9222-EP vref dac cpu v ea v eap v ead pmbus v ean vref = 1.563 mv/lsb g afe = 1, 2, 4, or 8 g eadc = 8mv/lsb 6-bit result eadc
UCD9222-EP www.ti.com slvsby1 ? october 2013 the differential feedback error voltage is defined as v ea = v eap ? v ean . an attenuator network using resistors r1 and r2 ( figure 12 ) should be used to ensure that v ea does not exceed the maximum value of vref when operating at the commanded voltage level. the commanded voltage level is determined by the pmbus settings described in the output voltage adjustment section. figure 12. input offset equivalent circuit voltage sense filtering conditioning should be provided on the eap and ean signals. figure 12 shows a divider network between the output voltage and the voltage sense input to the controller. the resistor divider is used to bring the output voltage within the dynamic range of the controller. when no attenuation is needed, r2 can be left open and the signal conditioned by the low-pass filter formed by r1 and c2. as with any power supply system, maximize the accuracy of the output voltage by sensing the voltage directly across an output capacitor as close to the load as possible. route the positive and negative differential sense signals as a balanced pair of traces or as a twisted pair cable back to the controller. put the divider network close to the controller. this ensures that there is low impedance driving the differential voltage sense signal from the voltage rail output back to the controller. the resistance of the divider network is a trade-off between power loss and minimizing interference susceptibility. a parallel resistance (r p ) of 1k to 4k ? is a good compromise. once rp is chosen, r1 and r2 can be determined from the following formulas. (2) it is recommended that a capacitor be placed across the lower resistor of the divider network. this acts as an additional pole in the compensation and as an anti-alias filter for the eadc. to be effective as an anti-alias filter, the corner frequency should be 35% to 40% of the switching frequency. then the capacitor is calculated as: (3) to obtain the best possible accuracy, the input resistance and offset current on the device should be considered when calculating the gain of a voltage divider between the output voltage and the ea sense inputs of the ucd9222. the input resistance and input offset current are specified in the parametric tables in this datasheet. v ea = v eap ? v ean in the equation below. (4) the effect of the offset current can be reduced by making the resistance of the divider network low. copyright ? 2013, texas instruments incorporated submit documentation feedback 21 product folder links : UCD9222-EP 2 1 2 ea out offset 1 2 1 2 1 2 1 2 ea ea r r r v v i r r r r r r r r r r = + ? ? ? ? + + + + ? ? ? ? sw p 1 c2 2 0.35 f r = p p 1 p 2 ea out r r k r r 1 k v where k vout_scale_loop v = = - = @ +vout -vout r1 r2 eapean c2 rin ioff
UCD9222-EP slvsby1 ? october 2013 www.ti.com digital compensator each voltage rail controller in the ucd9222 includes a digital compensator. the compensator consists of a nonlinear gain stage, followed by a digital filter consisting of a second order infinite impulse response (iir) filter section cascaded with a first order iir filter section. the texas instruments fusion digital power ? designer development tool can be used to assist in defining the compensator coefficients. the design tool allows the compensator to be described in terms of the pole frequencies, zero frequencies and gain desired for the control loop. in addition, the fusion digital power ? designer can be used to characterize the power stage so that the compensator coefficients can be chosen based on the total loop gain for each feedback system. the coefficients of the filter sections are generated through modeling the power stage and load. additionally, the ucd9222 has three banks of filter coefficients: bank-0 is used during the soft start/stop ramp or tracking; bank-1 is used while in regulation mode; and bank-2 is used when the measured output current is below the configured light load threshold. figure 13. digital compensator to calculate the values of the digital compensation filter continuous-time design parameters k dc , f z ands q z are entered into the fusion digital power designer software (or it calculates them automatically). where the compensating filter transfer function is (5) there are approximate limits the design parameters k dc , f z ands q z . though design parameters beyond these upper a lower bounds can be used to calculate the discrete-time filter coefficients, there will be significant round- off error when the continuous-time floating-point design parameters are converted to the discrete-time fixed-point integer coefficients to be downloaded to the controller. 22 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links : UCD9222-EP ( ) 2 2 z z z dc p2 s s 1 q h s k s s 1 + + w w = ? ? + ? w ?
UCD9222-EP www.ti.com slvsby1 ? october 2013 approximate design parameter units lower bound upper bound k dc 60 103 db f z 3 khz fsw/5 khz q z 0.1 5.0 n/a the nonlinear gain block allows a different gain to be applied to the system when the error voltage deviates from zero. typically limit 0 and limit 1 would be configured with negative values between ? 1 and ? 32 and limit 2 and limit 3 would be configured with positive values between 1 and 31. however, the gain thresholds do not have to be symmetrical. for example, the four limit registers could all be set to positive values causing the gain 0 value to set the gain for all negative errors and a nonlinear gain profile would be applied to only positive error voltages. the cascaded 1 st order filter section is used to generate the third zero and third pole. dpwm engine the output of the compensator feeds the high resolution dpwm engine. the dpwm engine produces the pulse width modulated gate drive output from the device. in operation, the compensator calculates the necessary duty cycle as a digital number representing a percentage from 0 to 100%. the duty cycle value is multiplied by the configured period to generate a comparator threshold value. this threshold is compared against the high speed switching period counter to generate the desired dpwm pulse width. this is shown in figure 14 . each dpwm engine can be synchronized to another dpwm engine or to an external sync signal via the syncin and syncout pins. configuration of the synchronization function is done through a mfr_specific pmbus command. see the dpwm synchronization section for more details. figure 14. dpwm engine rail/power stage configuration unlike many other products in the ucd92xx family, the ucd9222 does not support assigning power stages to arbitrary rails, or combining multiple power stages on the same rail. the ucd9222 supports up to two single- phase rails, and the channel number of each rail ? s dpwm output must match that of its eap/ean feedback inputs. copyright ? 2013, texas instruments incorporated submit documentation feedback 23 product folder links : UCD9222-EP high res ramp counter clk reset pwm gate drive output sysclk syncin eadc triggersyncout sr dpwm engine (1 of 2) switch period current balance adj compensator output (calculated duty cycle) eadc trigger threshold
UCD9222-EP slvsby1 ? october 2013 www.ti.com dpwm phase synchronization dpwm synchronization provides a method to link the timing between voltage rails controlled by the ucd92xx device--either internally or between devices. the configuration of the synchronization between rails is performed by the issuing the sync_config command. for details of issuing this command, see the ucd92xx pmbus command reference ( sluu337 ). the synchronization behavior can also be configured using the fusion digital power designer software. below is a summary of the function. each digital pulse width modulator (pwm) engine in the ucd92xx controller can accept a sync signal that resets the pwm ramp generator. the ramp generator can be set to free-run, accept a reset signal from another internal pwm engine, or accept a reset signal from the external syncin pin (ucd9222 only). in addition, each digital pwm engine can generate a phase delayed sync signal that can be directed to another pwm reset input or directed to the external syncout pin. in this way the pwm timers can be "daisy-chained" to set up the desired phase relationship between power stages. the pwm engine reset input can accept the following inputs table 6. sync trigger inputs none (free run) dpwm 1 dpwm 2 syncin pin when configuring a pwm engine to run synchronous to another internal pwm output, set the switching frequency of each pwm output to the same value using the frequency_switch pmbus command. set the time point where the controller samples the voltage to be regulated by setting the eadc_sample_trigger value to the minimum value (228-240 nsec before the end of the switching period). when configuring a pwm engine to run synchronous to run an external sync signal, the switching period must be set to be longer than the period of the sync signal by setting the value of the frequency_switch command to be lower than the frequency of the sync signal. this way the external sync signal will reset the pwm ramp counter before it is internally reset. in this operating condition, the error adc sample trigger time must be set to: (6) where f sw is the switching frequency set by frequency_switch and f sync is the minimum synchronization frequency. the factor of 0.95 is due to the 5% tolerance on the internal clock in the controller. this will ensure that the regulation voltage is sampled "just in time" to calculate the appropriate control effort for each switching period. this is shown in figure 15 . figure 15. relationship of eadc trigger to external sync 24 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links : UCD9222-EP eadc threshold pwm pulse compensated error sync-in convert adc sample and calculate compensated error insufficient time to convert adc sample early sync adc sample = period-eadc trigger previouscontrol effort sw sync 1 0.95 eadc_sample_trigger 248ns f f 3 - +
UCD9222-EP www.ti.com slvsby1 ? october 2013 if two rails share a common sync source other than the syncin pin, they must have the same delay. when the syncin pin is used as a sync source, the delay is applied using a different register (ev1) than when using the other sources (which use the phasetrig registers). using the ev1 register introduces delay in the control loop calculation that will introduce phase loss that must be taken into consideration when calculating the loop compensation. therefore, under most conditions it will be desirable to set the delay to zero for the pwm signal synchronized by the syncin pin. output current measurement pins cs1a and cs2a are used to measure either output current or inductor current in each of the controlled power stages. pmbus commands iout_cal_gain and iout_cal_offset are used to calibrate each measurement. see the ucd92xx pmbus command reference ( sluu337 ) for specifics on configuring this voltage to current conversion. when the measured current is outside the range of either the over-current or under-current fault threshold, a current limit fault is declared and the ucd9222 performs the pmbus configured fault recovery. adc current measurements are digitally averaged before they are compared against the over-current and under-current warning and fault thresholds. the output current is measured at a rate of one output rail per t iout microseconds. the current measurements are then passed through a digital smoothing filter to reduce noise on the signal and prevent false errors. the output of the smoothing filter asymptotically approaches the input value with a time constant that is approximately 3.5 times the sampling interval. table 7. output current filter time constants number of output current filter output rails sampling intervals ( s) time constant (ms) 1 200 0.7 2 400 1.4 this smoothed current measurement is used for output current fault detection; see the over-current detection section. the smoothed current measurement is also reported in response to a pmbus request for a current reading. current sense input filtering each power stage current is monitored by the device at the cs pins. the device monitors the current with a 12- bit adc and also monitors the current with a digitally programmable analog comparator. the comparator can be disabled by writing a zero to the fast_oc_fault_limit. because the current sense signal is both digitally sampled and compared to the programmable over-current threshold, it should be conditioned with an rc network acting as an anti-alias filter. if the comparator is disabled, the cs input should be filtered at 35% of the sampling rate. an rc network with this characteristic can be calculated as (7) where n rails is the number of rails configured and t iout is the sample period for the current sense inputs. therefore, when the comparator is not used, the recommended component values for the rc network are c = 10 nf and r = 35.7 k . when the fast over-current comparator is used, the filter corner frequency based on the adc sample rate may be too slow and a corner frequency that is a compromise between the requirements of fast over-current detection and attenuating aliased content in the sampled current must be sought. in this case, the filter corner frequency can be calculated based on the time to cross the over-current threshold. (8) where v oc_thres is the programmed oc comparator threshold, v cs_nom is the nominal cs voltage, v imon is the change in cs voltage due to an over-current fault and is the filter time constant. using the equation for the comparator voltage above, the rc network values can be calculated as copyright ? 2013, texas instruments incorporated submit documentation feedback 25 product folder links : UCD9222-EP t oc_thres cs_nom imon v v v (1 e ) - t = + d - rails iout n t r 0.45 c =
UCD9222-EP slvsby1 ? october 2013 www.ti.com (9) where t det is the time to cross the over-current comparator threshold. for t det = 10 s, v imon = 1.5v, v oc_thres = 2.0v and v cs_nom = 1.5v, the corner frequency is 6.4 khz and the recommended rc network component values are c = 10 nf and r = 2.49 k . over-current detection several mechanisms are provided to sense output current fault conditions. this allows for the design of power systems with multiple layers of protection. 1. integrated gate drivers such as the ucd72xx family can be used to generate the flt signal. the driver monitors the voltage drop across the high side fet and if it exceeds a resistor/voltage programmed threshold, the driver activates its fault output. a logic high signal on the flt input causes a hardware interrupt to the internal cpu, which then disables the dpwm output. this process takes about 14 microseconds. 2. inputs cs1a and cs2a each drive an internal analog comparator. these comparators can be used to detect the voltage output of a current sense circuit. each comparator has a separate threshold that can be set by the fast_oc_fault_limit pmbus command. though the command is specified in amperes, the hardware threshold is programmed with a value between 31mv and 2v in 64 steps. the relationship between amperes to sensed volts is configured by the iout_cal_gain command. when the current sense voltage exceeds the threshold, the corresponding dpwm output is driven low on the voltage rail with the fault. 3. each current sense input to the ucd9222 is also monitored by the 12-bit adc. each measured value is scaled using the iout_cal_gain and iout_cal_offset commands and then passed through a digital smoothing filter. the smoothed current measurements are compared to fault and warning limits set by the iout_oc_fault_limit and iout_oc_warn_limit commands. the action taken when an oc fault is detected is defined by the iout_oc_fault_response command. because the current measurement is averaged with a smoothing filter, the response time to an over-current condition depends on a combination of the time constant ( ) from table 7 , the recent measurement history, and how much the measured value exceeds the over-current limit. when the current steps from a current (i 1 ) that is less than the limit to a higher current (i 2 ) that is greater than the limit, the output of the smoothing filter is (10) at the point when i smoothed exceeds the limit, the smoothing filter lags time, t lag is (11) the worst case response time to an over-current condition is the sum of the sampling interval ( table 7 ) and the smoothing filter lag, t lag from equation 11 . current foldback mode when the measured output current exceeds the value specified by the iout_oc_fault_limit command, the ucd9222 attempts to continue to operate by reducing the output voltage in order to maintain the output current at the value set by iout_oc_fault_limit. this continues indefinitely as long as the output voltage remains above the minimum value specified by iout_oc_lv_fault_limit. if the output voltage is pulled down to less than that value, the device responds as programmed by the iout_oc_lv_fault_response command. input voltage monitoring the vinmon pin on the ucd9222 monitors the input voltage. the vinmon pin is monitored using the internal 12- bit adc which has a dynamic range of 0 to 2.5v. the fault thresholds for the input voltage are set using the vin_ov_fault_limit and vin_uv_fault_limit commands. the scaling for vin is set using the vin_scale_monitor command. 26 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links : UCD9222-EP 2 1 lag 2 lim it i i t ln i i ? ? - = t ? - ? ( ) ( ) ( ) t smoothed 1 2 1 i t i i i 1 e - t = + - - ( ) ( ) det imon imon oc_thres cs_nom t 1 r c ln v ln v v v = d - d - +
UCD9222-EP www.ti.com slvsby1 ? october 2013 input uv lockout the input supply lock-out voltage thresholds are configured with the vin_on and vin_off commands. when input supply voltage drops below the value set by vin_off, the device starts a normal soft stop ramp. when the input supply voltage drops below the voltage set by vin_uv_fault_limit, the device performs as configured by the vin_uv_fault_response command. for example, when the bias supply for the controller is derived from another source, the response code can be set to "continue" or "continue with delay," and the controller attempts to finish the soft stop ramp. if the bias voltages for the controller and gate driver are uncertain below some voltage, the user can set the uv fault limit to that voltage and specify the response code to be "shut down immediately," disabling all dpwm outputs. vin_off sets the voltage at which the output voltage soft-stop ramp is initiated, and vin_uv_fault_limit sets the voltage where power conversion is stopped. temperature monitoring the ucd9222 monitors temperature using the 12-bit adc. the adc12 is read every 100us and combined into a running sum. at the end of each 100ms monitoring interval, the ~1000 sample in the running sum are averaged together and the running sum is restarted. these averaged values are used to calculate the temperature from external temperature sensors. these same values may be read directly using the read_aux_adcs pmbus command. the averaged values are passed through an additional digital smoothing filter to further reduce the chance of reporting false over-temperature events. the smoothing filter has a time constant of 1.55 seconds. auxiliary adc input monitoring unused external temperature sensor inputs may be used for general-purpose analog monitoring. the read_aux_adcs pmbus command returns a block of four 16-bit values, each of which is the average of multiple raw measurements from the auxadc inputs. these auxadc inputs share usage with other signals such as temp1, temp2, vtrack, and iinmon. a value of 0 corresponds to 0.00v and a value of 65535 corresponds to 2.50v. unlike many other variables that can be monitored via pmbus, no mechanism is provided for adjusting the gain or offset of the aux adc measurements. when using the temperature sensor inputs as auxiliary adcs, the temperature warning and faults should be disabled to prevent shut-downs due to non-existent over-temperature conditions. soft start, soft stop ramp sequence the ucd9222 performs soft start and soft stop ramps under closed-loop control. performing a start or stop ramp or tracking is considered a separate operational mode. the other operational modes are normal regulation and light load regulation. each operational mode can be configured to have an independent loop gain and compensation. each set of loop gain coefficients is called a "bank" and is configured using the cla_gains pmbus command. start ramps are performed by waiting for the configured start delay ton_delay and then ramping the internal reference toward the commanded reference voltage at the rate specified by the ton_rise time and vout_command. the dpwm outputs are enabled when the internal ramp reference equals the preexisting voltage (pre-bias) on the output and the calculated dpwm pulse width exceeds the pulse width specified by driver_min_pulse. this ensures that a constant ramp rate is maintained, and that the ramp is completed at the same time it would be if there had not been a pre-bias condition. figure 16 shows the operation of soft-start ramps and soft-stop ramps. copyright ? 2013, texas instruments incorporated submit documentation feedback 27 product folder links : UCD9222-EP
UCD9222-EP slvsby1 ? october 2013 www.ti.com figure 16. start and stop ramps when a voltage rail is in its idle state, the dpwm outputs are disabled, and the differential voltage on the eap/ean pins are monitored by the controller. during idle the vref dac is adjusted to match the feedback voltage. if there is a pre-bias (that is, a non-zero voltage on the regulated output), then the device can begin the start ramp from that voltage with a minimum of disturbance. this is done by calculating the duty cycle that is required to match the measured voltage on the rail. nominally this is calculated as vout / vin. if the pre-bias voltage on the output requires a smaller pulse width than the driver can deliver, as defined by the driver_min_pulse pmbus command, then the start ramp is delayed until the internal ramp reference voltage has increased to the point where the required duty cycle exceeds the specified minimum duty. once a soft start/stop ramp has begun, the output is controlled by adjusting the vref dac at a fixed rate and allowing the digital compensator control engine to generate a duty cycle based on the error. the vref dac adjustments are made at a rate of 10 khz and are based on the ton_rise or toff_fall pmbus configuration parameters. although the presence of a pre-bias voltage or a specified minimum dpwm pulse width affects the time when the dpwm signals become active, the time from when the controller starts processing the turn-on command to the time when it reaches regulation is ton_delay plus ton_rise, regardless of the pre-bias or minimum duty cycle. during a normal ramp (i.e. no tracking, no current limiting events and no eadc saturation), the set point slews at a pre-calculated rate based on the commanded output voltage and ton_rise. under closed loop control, the compensator follows this ramp up to the regulation point. because the eadc in the controller has a limited range, it may saturate due to a large transient during a start/stop ramp. if this occurs, the controller overrides the calculated set point ramp value, and adjusts the vref dac in the direction to minimize the error. it continues to step the vref dac in this direction until the eadc comes out of saturation. once it is out of saturation, the start ramp continues, but from this new set point voltage; and therefore, has an impact on the ramp time. non-volatile memory error correction coding the ucd9222 uses error correcting code (ecc) to improve data integrity and provide high reliability storage of data flash contents. ecc uses dedicated hardware to generate extra check bits for the user data as it is written into the flash memory. this adds an additional six bits to each 32-bit memory word stored into the flash array. these extra check bits, along with the hardware ecc algorithm, allow for any single bit error to be detected and corrected when the data flash is read. 28 submit documentation feedback copyright ? 2013, texas instruments incorporated product folder links : UCD9222-EP
UCD9222-EP www.ti.com slvsby1 ? october 2013 application information automatic system identification ( auto-id ? ) by using digital circuits to create the control function for a switch-mode power supply, additional features can be implemented. one of those features is the measurement of the open loop gain and stability margin of the power supply without the use of external test equipment. this capability is called automatic system identification or auto-id ? . to identify the frequency response, the ucd9222 internally synthesizes a sine wave signal and injects it into the loop at the vref dac. this signal excites the system, and the closed-loop response to that excitation can be measured at another point in the loop. the ucd9222 measures the response to the excitation at the output of the digital compensator. from the closed-loop response, the open-loop transfer function is calculated. the open-loop transfer function may be calculated from the closed-loop response. note that since the compensator and dpwm are digital, their transfer functions are known exactly and can be divided out of the measured open-loop gain. in this way the ucd9222 can accurately measure the power stage/load plant transfer function in situ (in place), on the factory floor or in an end equipment application and send the measurement data back to a host through the pmbus interface without the need for external test equipment. details of the auto-id ? pmbus measurement commands can be found in the ucd92xx pmbus command reference ( sluu337 ). data logging the ucd9222 maintains a data log in non-volatile memory. this log tracks the peak internal and external temperature sensor measurements, peak current measurements and fault history. the pmbus commands and data format for the data logging can be found in the ucd92xx pmbus command reference ( sluu337 ). copyright ? 2013, texas instruments incorporated submit documentation feedback 29 product folder links : UCD9222-EP
package option addendum www.ti.com 3-nov-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples ucd9222wrgzrep active vqfn rgz 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -55 to 115 ucd9222ep v62/13622-01xe active vqfn rgz 48 2500 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -55 to 115 ucd9222ep (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 3-nov-2013 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of UCD9222-EP : ? catalog: ucd9222 note: qualified version definitions: ? catalog - ti's standard catalog product
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant ucd9222wrgzrep vqfn rgz 48 2500 330.0 16.4 7.3 7.3 1.1 12.0 16.0 q2 package materials information www.ti.com 25-mar-2015 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) ucd9222wrgzrep vqfn rgz 48 2500 367.0 367.0 38.0 package materials information www.ti.com 25-mar-2015 pack materials-page 2

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